In electronics, a multiplexer (“MUX”) is a device that performs the process of multiplexing, i.e. selecting one of a number of signal inputs to provide a single signal output. The selection of a signal input is accomplished by a selector input which may be a single line if the MUX has only two inputs and which has multiple lines if the MUX has more than two inputs. In general, a MUX having 2n inputs has n select lines (“select line bus”).
Various input signals can be applied to the inputs of a MUX, including analog and digital signals. If all of the input signals are analog signals, the MUX may be referred to as an “analog MUX”, and if all of the input signals are digital signals, the MUX may be referred to as a “digital MUX.”
One area of technology which often uses an analog MUX is that of data acquisition (“DAQ”). DAQ systems convert analog electrical signals representing real world physical conditions into digital electrical signals for subsequent digital processing using an analog-to-digital converter (“ADC”) which samples (or oversamples) the analog input signal to provide a digital output representing the magnitude of the analog input at the time of the sampling. Since accurate and high-speed ADCs are relatively expensive, a MUX is often used to coordinate multiple input “channels” to be input into an ADC.
FIG. 1 illustrates a conventional DAQ circuit 10 which may be implemented as a packaged integrated circuit 12. The DAQ circuit 10 includes an analog MUX 14 provided with analog input channels AIN(0)-AIN(2n−1) and a selector input S. The DAQ circuit 10 further includes an ADC 16 having an input coupled to the analog output of MUX 14 to provide a digital output DOUT.
The ADC 16 typically operates on the principle of oversampling by sampling the signal at the output of the MUX 14 with a sampling frequency that is significantly greater than twice the highest frequency of the signal being sampled. The conversion of the analog signal to a digital signal is known as a “convert.” The channel of the MUX 14 is selected by the CHSEL( ) (channel select) bus which, in this example, is an n-line bus having lines CHSEL(0)-CHSEL(n−1). As a more concrete example, if n=4, the CHSEL( ) bus is a four-line bus and can control a 24=16 channel MUX 14.
With continuing reference to FIG. 1, an optional register 18 may be provided as part of the channel select circuitry. A first example register 18A is shown in FIG. 2A and a second example register 18B is shown in FIG. 2B. As will be discussed, these registers allow for a limited amount of user configuration of the channel select sequence for the MUX 14.
In FIG. 2A, a 4-bit register 18A of the prior art is illustrated. This register can be used to configure the channel select sequence of MUX 14 in a “manual” mode. For example, a user can input the channel number to be selected by writing the channel number to the register. In this example, channel AIN(9) has been selected by entering the binary number “1001” at a time t and, at a time t+1 (typically the next clock cycle), the ADC converts the signal sampled on channel AIN(9). Alternatively, register 18A can be used to configure the channel select sequence of MUX 14 in a “scan channels” mode. For example, a user can input a maximum channel number M by writing the channel number to the register such that the channels are scanned from channel AIN(0) to AIN(M) in a repetitive fashion for conversion by the ADC. The sequence can be repeated without further instruction.
FIG. 2B illustrates an alternative register 18B which, in this example, is 16 bits long. Register 18B can be used to scan a custom set of channels. In this example, channels AIN(1), AIN(3), AIN(6), AIN(7), AIN(9), AIN(11), AIN(14), AIN(15) have been selected. The ADC converts these channels in ascending order, and the sequence may be repeated without further instruction.
A problem encountered with the use of registers in DAQ circuits of the prior art is that the configurability of the channel select pattern is quite limited. For example, prior art DAQ circuits, even if they have a scanning mode, only scan in an ascending order. Furthermore, the channel select patterns are quite limited and do not account for the needs of customers who wish to convert analog signals of different frequencies. This can result in gross oversampling of low frequency input signals and, therefore, less efficient system performance.
Another problem encountered with conventional DAQ circuit such as the one illustrated in FIG. 1 is that they create significant overhead with respect to a microcontroller or digital signal processor (“DSP”) writing to the register. That is, each time a different channel of the MUX 14 is selected, an external processor must make the necessary calculations and input the channel select signal to select the proper channel. Since the external processor is often involved in other processes, this is a significant load on the processor any may tie up some of the system busses.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.